\chapter{Conclusion and Future Work}\label{chapter:con}

Integrating billions of transistors on a single chip with nano-scale
transistors has resulted in great challenges for chip designers. One of these
challenges is that the pace of productivity gains has not kept up to address
the increases in design complexity. Consequently, we have seen a recent trend
of moving design abstraction to a higher level, with an emphasis on
\textbf{Electronic System Level (ESL)} design methodologies. A very important
component of ESL is raising the level of abstraction of hardware design.
High-level synthesis (HLS) provides this component by providing automation to
generate optimized hardware from a high-level description of the function or
algorithm to be implemented in hardware. HLS generates a cycle-accurate
specification at the register-transfer level (RTL) that is then used in
existing ASIC or FPGA design methodologies. Commercial high-level synthesis
tools~\cite{HLS:newbook} have recently gained a lot of attention as evidenced
in recent conference HLS workshops, conference panels and publications that
track the industry.

Previous work on statistical high-level synthesis focused on augmenting the
synthesis flow to be variation-aware. The work presented in this thesis tries
to extend such statistical design methodology to more aspects of the design
hierarchy. Towards this effort, new optimization techniques for statistical
high-level synthesis are first presented. New design styles with cycle stealing
on latches and multi-supply/threshold voltage components are then explored to
further mitigate the impact of process variability in high-level synthesis.
More importantly, initial explorations on combining statistical behavioral
synthesis with the new emerging 3D integration technology show promising
results. Overall, the presented work makes an important contribution to move
from the deterministic design methodologies to the statistical design
methodologies in high level synthesis and hardware/software co-synthesis.

Nevertheless, the work presented in this thesis constitutes a partial
foundation of incorporating statistical analysis at higher level of the design
hierarchy. Many topics could be further explored in the future, by extending
the statistical design methodology to cover broader areas, more technologies
with various design targets.

Although process variations are considered as a major source of unreliability,
other major reliability concerns faced by designers of systems include aging
effects and increasing on-chip temperature due to increasing power density.
Chapter~\ref{chapter:nbti} presented an initial exploration of the NBTI effects
within the framework statistical high-level synthesis. Whether the framework
can be extended to model other effects with accurate modeling, remains to be
explored.

Integrating statistical high-level synthesis into the design of 3D ICs helps
push forward both ESL design methodologies and the 3D IC technologies.
High-level synthesis has shown great potentials in serving as a tuning knob
during the system-level design exploration of 3D SoCs. In the future,
statistical synthesis could be employed as a key component in the system-level
design process, by balancing the trade-offs between performance, power, thermal
and parametric yields, and reducing the overall system cost through exploring
the even enlarged design space. Future work in this direction might consist of
a comprehensive statistical system-level design tool for 3D SoCs, mapping
large-scale behavior descriptions of circuits to high-quality 3D
implementations to be built on unreliable silicon fabrics.
